Exemplary embodiments relate to an analog integrated circuit, and more particularly, relate to a bias circuit of an analog integrated circuit.
A switched-capacitor circuit may be widely used to design analog integrated circuits such as an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a sigma-delta analog-to-digital converter, and the like. The switched-capacitor circuit may necessitate an excellent settling characteristic to secure an exact operation of the analog integrated circuit.
A settling time of the settling characteristic of the switched-capacitor circuit may be reduced by increasing a bandwidth and a slew rate. In particular, if the slew rate is low, the settling time of the switched-capacitor circuit may increase due to a long slew time.